Invert sense of SLB class bit

linas linas at
Thu Sep 8 08:28:16 EST 2005

On Tue, Sep 06, 2005 at 05:03:22PM -0400, Sonny Rao was heard to remark:
> On Tue, Sep 06, 2005 at 02:59:47PM +1000, David Gibson wrote:
> > Currently, we set the class bit in kernel SLB entries, and clear it on
> > user SLB entries.  On POWER5, ERAT entries created in real mode have
> > the class bit clear.  So to avoid flushing kernel ERAT entries on each
> > context switch, this patch inverts our usage of the class bit, setting
> > it on user SLB entries and clearing it on kernel SLB entries.
> > 
> > Booted on POWER5 and G5.

Antonb had been talking about something like this more than a year 
ago ... as there was code added to not flush the 0xc segment.  
Did that code not work? Or did it get broken? Or was it never 
submitted upstream?

Or is this a patch to not flush kernel erats on machines with 
more than 16GB memory?


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