[PATCH] [2/4] PPC64: Remove TCE/DART dependency on 4K PAGE_SIZE
Olof Johansson
olof at lixom.net
Wed Aug 10 06:22:45 EST 2005
There are potential cases in the future where the IOMMU might be mapping smaller
pages than the regular MMU is using. Keep the allocator working on MMU pagesizes,
but the low-level mapping functions need to map more than one TCE entry per page
to deal with this.
Signed-off-by: Olof Johansson <olof at lixom.net>
Index: gr_work/arch/ppc64/kernel/pSeries_iommu.c
===================================================================
--- gr_work.orig/arch/ppc64/kernel/pSeries_iommu.c 2005-08-08 11:09:02.977599596 -0500
+++ gr_work/arch/ppc64/kernel/pSeries_iommu.c 2005-08-08 11:09:21.485465685 -0500
@@ -59,6 +59,9 @@ static void tce_build_pSeries(struct iom
union tce_entry t;
union tce_entry *tp;
+ index <<= TCE_PAGE_FACTOR;
+ npages <<= TCE_PAGE_FACTOR;
+
t.te_word = 0;
t.te_rdwr = 1; // Read allowed
@@ -69,11 +72,11 @@ static void tce_build_pSeries(struct iom
while (npages--) {
/* can't move this out since we might cross LMB boundary */
- t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
+ t.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
tp->te_word = t.te_word;
- uaddr += PAGE_SIZE;
+ uaddr += TCE_PAGE_SIZE;
tp++;
}
}
@@ -84,6 +87,9 @@ static void tce_free_pSeries(struct iomm
union tce_entry t;
union tce_entry *tp;
+ npages <<= TCE_PAGE_FACTOR;
+ index <<= TCE_PAGE_FACTOR;
+
t.te_word = 0;
tp = ((union tce_entry *)tbl->it_base) + index;
@@ -103,7 +109,7 @@ static void tce_build_pSeriesLP(struct i
union tce_entry tce;
tce.te_word = 0;
- tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
+ tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
tce.te_rdwr = 1;
if (direction != DMA_TO_DEVICE)
tce.te_pciwr = 1;
@@ -136,6 +142,9 @@ static void tce_buildmulti_pSeriesLP(str
union tce_entry tce, *tcep;
long l, limit;
+ tcenum <<= TCE_PAGE_FACTOR;
+ npages <<= TCE_PAGE_FACTOR;
+
if (npages == 1)
return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
direction);
@@ -155,7 +164,7 @@ static void tce_buildmulti_pSeriesLP(str
}
tce.te_word = 0;
- tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;
+ tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
tce.te_rdwr = 1;
if (direction != DMA_TO_DEVICE)
tce.te_pciwr = 1;
@@ -166,7 +175,7 @@ static void tce_buildmulti_pSeriesLP(str
* Set up the page with TCE data, looping through and setting
* the values.
*/
- limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));
+ limit = min_t(long, npages, 4096/sizeof(union tce_entry));
for (l = 0; l < limit; l++) {
tcep[l] = tce;
@@ -196,6 +205,9 @@ static void tce_free_pSeriesLP(struct io
u64 rc;
union tce_entry tce;
+ tcenum <<= TCE_PAGE_FACTOR;
+ npages <<= TCE_PAGE_FACTOR;
+
tce.te_word = 0;
while (npages--) {
@@ -221,6 +233,9 @@ static void tce_freemulti_pSeriesLP(stru
u64 rc;
union tce_entry tce;
+ tcenum <<= TCE_PAGE_FACTOR;
+ npages <<= TCE_PAGE_FACTOR;
+
tce.te_word = 0;
rc = plpar_tce_stuff((u64)tbl->it_index,
Index: gr_work/include/asm-ppc64/tce.h
===================================================================
--- gr_work.orig/include/asm-ppc64/tce.h 2005-08-08 11:09:02.978599438 -0500
+++ gr_work/include/asm-ppc64/tce.h 2005-08-08 11:09:21.486465527 -0500
@@ -29,6 +29,13 @@
#define TCE_VB 0
#define TCE_PCI 1
+/* TCE page size is 4096 bytes (1 << 12) */
+
+#define TCE_SHIFT 12
+#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
+#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
+
+
/* tce_entry
* Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
* abstracted so layout is irrelevant.
Index: gr_work/arch/ppc64/kernel/u3_iommu.c
===================================================================
--- gr_work.orig/arch/ppc64/kernel/u3_iommu.c 2005-08-08 11:09:02.977599596 -0500
+++ gr_work/arch/ppc64/kernel/u3_iommu.c 2005-08-08 11:09:21.488465210 -0500
@@ -125,18 +125,21 @@ static void dart_build(struct iommu_tabl
DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
+ index <<= DART_PAGE_FACTOR;
+ npages <<= DART_PAGE_FACTOR;
+
dp = ((unsigned int*)tbl->it_base) + index;
/* On U3, all memory is contigous, so we can move this
* out of the loop.
*/
while (npages--) {
- rpn = virt_to_abs(uaddr) >> PAGE_SHIFT;
+ rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
rpn++;
- uaddr += PAGE_SIZE;
+ uaddr += DART_PAGE_SIZE;
}
dart_dirty = 1;
@@ -154,6 +157,9 @@ static void dart_free(struct iommu_table
DBG("dart: free at: %lx, %lx\n", index, npages);
+ index <<= DART_PAGE_FACTOR;
+ npages <<= DART_PAGE_FACTOR;
+
dp = ((unsigned int *)tbl->it_base) + index;
while (npages--)
@@ -182,10 +188,10 @@ static int dart_init(struct device_node
* that to work around what looks like a problem with the HT bridge
* prefetching into invalid pages and corrupting data
*/
- tmp = lmb_alloc(PAGE_SIZE, PAGE_SIZE);
+ tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
if (!tmp)
panic("U3-DART: Cannot allocate spare page!");
- dart_emptyval = DARTMAP_VALID | ((tmp >> PAGE_SHIFT) & DARTMAP_RPNMASK);
+ dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & DARTMAP_RPNMASK);
/* Map in DART registers. FIXME: Use device node to get base address */
dart = ioremap(DART_BASE, 0x7000);
@@ -196,8 +202,8 @@ static int dart_init(struct device_node
* table size and enable bit
*/
regword = DARTCNTL_ENABLE |
- ((dart_tablebase >> PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |
- (((dart_tablesize >> PAGE_SHIFT) & DARTCNTL_SIZE_MASK)
+ ((dart_tablebase >> DART_PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |
+ (((dart_tablesize >> DART_PAGE_SHIFT) & DARTCNTL_SIZE_MASK)
<< DARTCNTL_SIZE_SHIFT);
dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);
Index: gr_work/include/asm-ppc64/dart.h
===================================================================
--- gr_work.orig/include/asm-ppc64/dart.h 2005-08-08 11:09:02.978599438 -0500
+++ gr_work/include/asm-ppc64/dart.h 2005-08-08 11:09:21.489465051 -0500
@@ -52,5 +52,9 @@
#define DARTMAP_RPNMASK 0x00ffffff
+#define DART_SHIFT 12
+#define DART_PAGE_SIZE (1 << DART_SHIFT)
+#define DART_PAGE_FACTOR (PAGE_SHIFT - DART_SHIFT)
+
#endif
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