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bus cycle, but we write some wrong data. This only happens if we have
FEC+ATA active at the same time.

Increasing the ATA priorities above the FEC priorities gives us FEC
errors, but the external peripheral works.


I'm sure others have similar problems. Did any of you change the
priority setting of these tasks to be able to run her/his hardware? Is
this related to the XLB pipelining problem as described in the errata
and previous mails in this list? Does anybody know if this problem is
fixed in newer revisions of the chip? Could be disabling pipelining
and waiting for TIP to go away help as well?


Thanks for any help.


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