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Sun Nov 23 10:02:55 EST 2008

bus cycle, but we write some wrong data. This only happens if we have

FEC+ATA active at the same time.

Increasing the ATA priorities above the FEC priorities gives us FEC

errors, but the external peripheral works.

I'm sure others have similar problems. Did any of you change the

priority setting of these tasks to be able to run her/his hardware? Is

this related to the XLB pipelining problem as described in the errata

and previous mails in this list? Does anybody know if this problem is

fixed in newer revisions of the chip? Could be disabling pipelining

and waiting for TIP to go away help as well?

Thanks for any help.

Roman

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<DIV><FONT face=3DArial><PRE><SPAN class=3D937020410-09122008><FONT =
size=3D2>Hi,</FONT></SPAN></PRE><PRE><SPAN =
class=3D937020410-09122008><FONT size=3D2>We have discovered we have the =
same issu you had on one of our systems.</FONT></SPAN></PRE><PRE><SPAN =
class=3D937020410-09122008><FONT size=3D2>Did you fix it on your side =
?</FONT></SPAN></PRE><PRE><SPAN class=3D937020410-09122008><FONT =
size=3D2></FONT></SPAN>&nbsp;</PRE><PRE><SPAN =
class=3D937020410-09122008><FONT =
size=3D2></FONT></SPAN>&nbsp;</PRE><PRE><SPAN =
class=3D937020410-09122008><FONT =
size=3D2>Regards,</FONT></SPAN></PRE><PRE><FONT =
size=3D2></FONT>&nbsp;</PRE><PRE><FONT =
size=3D2></FONT>&nbsp;</PRE><PRE><FONT size=3D2>Hello,

We've got the following problem:

MPC5200CBV400 L25R Rev 2

Using the DENX 2.4.25 with FEC and ATA DMA, BAPI 2.2, Prios are set to
FEC 6/5 and ATA 4/3 (RX/TX). This causes the FEC task to interrupt the
ATA task (default).

We try to load both tasks by transferring data from the ATA disk to
the Ethernet, e.g. by using FTP.

At the same time we write to some peripheral on the LocalPlus from
within a cyclic timer tasklet.