[U-Boot-Users] mpc5121 cache coherency

John Rigby jcrigby at gmail.com
Thu Jun 19 05:38:49 EST 2008

Unlike other SOCs with e300 cores the 5121 is not cache coherent.  The
problem is an internal bridge that the processor can not snoop across.

On Wed, Jun 18, 2008 at 1:29 PM, Kenneth Johansson <kenneth at southpole.se> wrote:
> I have  tried to speed up u-boot by turning on I/D cache during boot.
> It sort of works and gives quite a boost but I'm having problems with
> the ethernet driver that no longer works.
> What I'm seeing is that the cpu do not notice the ethernet hardwares
> updates that is located in DRAM. Basically what is expected from a cache
> incoherent system.
> Now my question is should not the e300 core detect writes to the DRAM
> and reload the cached data ??
> ---
> To get cache working I'm turning on the MMU and program some BAT
> registers to a 1-1 mapping where only DRAM has cache on and all other
> memory regions like the IMMR, flash ... has cache off.
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