Problem booting Linux 2.6 on Virtex-4

[Stephen Neuendorffer]

What kernel version are you targeting? Are you using arch/powerpc or arch/ppc?  V4 has a data cache errata, which isn't currently in mainline arch/powerpc.

        if((mfpvr() & 0xfffff000) == 0x20011000) {
            /* PPC errata 213: only for Virtex-4 FX */
            __asm__("mfccr0  0\n\t"
                    "oris    0,0,0x50000000 at h\n\t"
                    "mtccr0  0"
                    : : : "0");
        }

Steve

> -----Original Message-----
> From: linuxppc-embedded-bounces+stephen=neuendorffer.name at ozlabs.org [mailto:linuxppc-embedded-
> bounces+stephen=neuendorffer.name at ozlabs.org] On Behalf Of David Baird
> Sent: Monday, January 14, 2008 12:12 PM
> To: linuxppc-embedded at ozlabs.org
> Subject: Re: Problem booting Linux 2.6 on Virtex-4
> 
> On Jan 14, 2008 1:37 AM, Enno Lübbers <enno.luebbers at upb.de> wrote:
> > Hello David,
> >
> > Am 14.01.2008 um 06:12 schrieb David Baird:
> >
> > > I'm having trouble with getting Linux to boot farther than early_init.
> > > [...]
> > > So, I experimented further and discovered that different memory
> > > regions seem to be aliased on to each other every 2*32*256 bytes.
> >
> >
> > This sounds either like a wrong programming of an BRx/ORx memory
> > controller register pair (which, AFAIK, the PPC405 does not have), or
> > like a messed up address map in EDK. My guess is that an optimized/
> > sloppy implementation of the address decoder for some peripheral in an
> > EDK system could produce something like you described; or there's a
> > block RAM that's attached to a controller in the wrong way; or the
> > bank/address parameters of the DDR controller don't match the physical
> > setup... there's a lot that can go wrong obviously on a configurable
> > SoC.
> 
> What has been confusing me is that I am unable to reproduce the
> problem in real mode.  I can only reproduce the problem in virtual
> mode.  This leads me to believe, perhaps mistakenly, that the hardware
> is implemented okay.  OTOH, neither can I see anything wrong with the
> software.
> 
> > Can you be more specific about your hardware platform? Is this a
> > reference design? What board are you using?
> 
> I am currently testing code on the ML403 evaluation board.  I used the
> Base System Builder in EDK to create the hardware design and DDR SDRAM
> is being used as the main RAM starting at address 0x00000000 and also
> with OCM BRAM mapped at the very end of the address space (so that
> 0xfffffffc can contain code to execute on startup).
> 
> I am now trying to experiment with the hardware and see if I can find
> a hardware reference design.  I will let you know what I figure out.
> 
> -David
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