TLB Miss booting linux kernel on ppc 405

[Ricardo Ayres Severo]

Here are the srr dump:
  srr0: c0002218
  srr1: 00021030
  srr2: 00001154
  srr3: 00000000

On Feb 13, 2008 3:51 PM, David Baird <dhbaird at gmail.com> wrote:
> On Feb 13, 2008 10:38 AM, Ricardo Ayres Severo <severo.ricardo at gmail.com> wrote:
> > I tracked the kernel execution using step one instruction (si) on gdb
> > and matching the jumps with the System.map.
> > It is a Data TLB Miss and this is the register dump after the miss occurs:
> >
> >     r1: 00502090
> >     r2: 0000000f
> >     r3: c00003c0
> >     r4: c0000000
> >     r5: 00000000
> >     r6: 00000000
> >     r7: 74747955
> >     r8: 4c302c39
> >     r9: 00000000
> >     pc: 00001100
> >     lr: 00000018
>
> Can you also past the special registers (srrd in XMD)?  I am very
> curious about SRR0 and SRR1 and maybe some of the others.
>
> > Now I'm checking the PPC cache configurations on XPS, because when
> > treating the DTLB Miss Exception a Machine Check Exception occurs when
> > it works with L1. Does this makes sense or am I confusing things?
>
> Too soon for me to tell :-)
>
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-- 
Ricardo Ayres Severo <severo.ricardo at gmail.com>