The question about the relocate_code on u-boot for MPC8360?

[Paul Gortmaker]

On 8/30/07, 郭劲 <guojin02 at tsinghua.org.cn> wrote:
>
> Hi, Friends,
>
>
> I am debuging the u-boot on freescale MPC8360, the version of u-boot is 1.2.0, the
> code on flash is OK,but the code from FLASH to DDR is broken, that is, after the
> relocate_code function, the u-boot start again. I tested the DDR on u-boot, it's
> OK. I was wondering that hot to deal with this problem? follow is the COM output
> from u-boot. Thanks.
>

I think you will find that the default 1.2.0 tree does not contain the
support for newer 8360MDS boards with the rev2 CPU and the DDR2.
There were git commits post 1.2.0 that added support for these -- for
example:

        Fix two bugs for MPC83xx DDR2 controller SPD Init
        commit 6fbf261f8df294e589cfadebebe5468e3c0f29e9

        mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx
        commit d61853cf2472e0b8bcbd131461a93d1c49ff0c1f

There were also some DDR2 related changes that came in with the
mpc832xMDS patches.

Paul.




>
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> U-Boot 1.2.0 (Aug 29 2007 - 20:50:37) MPC83XX
>
> Clock configuration:
>   Coherent System Bus:  264 MHz
>   Core:                 528 MHz
>   QE:                   198 MHz
>   Local Bus Controller: 264 MHz
>   Local Bus:             66 MHz
>   DDR:                  264 MHz
>   DDR Secondary:        264 MHz
>   SEC:                   88 MHz
>   I2C1:                 264 MHz
>   I2C2:                 264 MHz
> CPU: Rev: Unknown guojing modified source code
> Rev: 20 at 528 MHz
> Board: Freescale MPC8360EMDS
> I2C:   ready
> DRAM:
>    SDRAM on Local Bus: 64 MB
>    DDR RAM: 256 MB
> DDR test phase 1:
> DDR test phase 2:
> DDR test passed.
> init_sequence finished
> begin set up a new stack
> beginning memcpy
> ended memcpy,beginning relocate_code
>
>
> U-Boot 1.2.0 (Aug 29 2007 - 20:50:37) MPC83XX
>
> Clock configuration:
>   Coherent System Bus:  264 MHz
>   Core:                 528 MHz
>   QE:                   198 MHz
>   Local Bus Controller: 264 MHz
>   Local Bus:             66 MHz
>   DDR:                  264 MHz
>   DDR Secondary:        264 MHz
>   SEC:                   88 MHz
>   I2C1:                 264 MHz
>   I2C2:                 264 MHz
> CPU: Rev: Unknown guojing modified source code
> Rev: 20 at 528 MHz
> Board: Freescale MPC8360EMDS
> I2C:   ready
> DRAM:
>    SDRAM on Local Bus: 64 MB
>    DDR RAM: 256 MB
> DDR test phase 1:
> DDR test phase 2:
> DDR test passed.
> init_sequence finished
> begin set up a new stack
> beginning memcpy
> ended memcpy,beginning relocate_code
>
>
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