Xilinx FX60

[Wood, Robert (GE Indust, GE Fanuc)]

In the UCF we tightened up the spec for the core clock by around 15%
rather than 10%.

The resets were given a max delay constraint and physical location.

Some examples taken from our UCF file.

NET EC_FPGA_RESET_N TIG;


NET "RSTC405RESETSYS" TPTHRU = RST_GRP;
NET "RSTC405RESETCHIP" TPTHRU = RST_GRP;
NET "RSTC405RESETCORE" TPTHRU = RST_GRP;
NET "C405RSTSYSRESETREQ" TPTHRU = RST_GRP;
NET "C405RSTCHIPRESETREQ" TPTHRU = RST_GRP;
NET "C405RSTCORERESETREQ" TPTHRU = RST_GRP;
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; 

# Constrain Placement on PPC:
INST "ppc405_0/ppc405_0/PPC405_i" LOC = PPC405_X1Y0;

# Constrain the Xilinx IP reset block close to the PPC:
INST reset_block* AREA_GROUP="RESET_BLOCK_GRP";
AREA_GROUP "RESET_BLOCK_GRP" RANGE=SLICE_X94Y81:SLICE_X109Y72;

INST "reset_block/reset_block/Rstc405resetcore" TNM =
"reset_block/reset_block/Rstc405resetcore";
INST "reset_block/reset_block/Rstc405resetsys"  TNM =
"reset_block/reset_block/Rstc405resetsys";
INST "reset_block/reset_block/Rstc405resetchip" TNM =
"reset_block/reset_block/Rstc405resetchip";
INST "ppc405_0/ppc405_0/PPC405_i" TNM = "ppc405_0/ppc405_0/PPC405_i";
TIMESPEC "TS_reset_core" = FROM
"reset_block/reset_block/Rstc405resetcore" TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;
TIMESPEC "TS_reset_sys"  = FROM
"reset_block/reset_block/Rstc405resetsys"  TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;
TIMESPEC "TS_reset_chip" = FROM
"reset_block/reset_block/Rstc405resetchip" TO
"ppc405_0/ppc405_0/PPC405_i" 2.0 ns;

Robert Wood
GEFanuc Sensor Processing
5430 Canotek Road
Ottawa, Ontario
Canada K1J 9G2
613-749-9241 x270
 
-----Original Message-----
From: Robert Woodworth [mailto:rwoodworth at securics.com] 
Sent: Wednesday, September 05, 2007 3:31 PM
To: Wood, Robert (GE Indust, GE Fanuc)
Cc: linuxppc-embedded at ozlabs.org
Subject: RE: Xilinx FX60

On Wed, 2007-09-05 at 14:56 -0400, Wood, Robert (GE Indust, GE Fanuc)
wrote:
> We've been using Virtex 2 PRO with dual cores. We found it necessary
to
> very tightly constrain clocks and resets. Also, constrain the reset
> block to adjacent to the ports on the PPC.

What constraints did you tighten?? EDK or ISE?


> Another lightly documented feature is that the core clock must be an
> integer multiple of the PLB clock, say 300MHz/100MHz.
> 
> Robert Wood
> GEFanuc Sensor Processing
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> 613-749-9241 x270
>  
> 
> -----Original Message-----
> From: linuxppc-embedded-bounces+rwood=ics-ltd.com at ozlabs.org
> [mailto:linuxppc-embedded-bounces+rwood=ics-ltd.com at ozlabs.org] On
> Behalf Of Robert Woodworth
> Sent: Wednesday, September 05, 2007 2:42 PM
> To: linuxppc-embedded at ozlabs.org
> Subject: Xilinx FX60
> 
> After achieving complete success with my Linux kernel on the ML403,
I've
> now started to build a kernel for my real target board with a
> Virtex4-FX60 (dual PPC cores)
> 
> Has anyone built a kernel for a dual core PPC Virtex?  I have found
very
> little docs on how to architect software for the dual-core PPC's.  
> Will SMP Linux work on this platform?  What would the bus setup be?
> 
> 
> 
> My kernel is partially booting, some of the time... I'm mystified by
the
> situation.  One time, I get all the happy boot messages through the
> UARTLite port, then the next reboot it stops at "Now booting the
kernel"
> I'm only getting about 10% successful boots......
> 
> 
> My EDK setup is as follows;  I've disconnected the second PPC from the
> PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB,
UARTLite
> on OPB.
> 
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