Xilinx FX60

[Robert Woodworth]

On Wed, 2007-09-05 at 14:56 -0400, Wood, Robert (GE Indust, GE Fanuc)
wrote:
> We've been using Virtex 2 PRO with dual cores. We found it necessary to
> very tightly constrain clocks and resets. Also, constrain the reset
> block to adjacent to the ports on the PPC.

What constraints did you tighten?? EDK or ISE?


> Another lightly documented feature is that the core clock must be an
> integer multiple of the PLB clock, say 300MHz/100MHz.
> 
> Robert Wood
> GEFanuc Sensor Processing
> 5430 Canotek Road
> Ottawa, Ontario
> Canada K1J 9G2
> 613-749-9241 x270
>  
> 
> -----Original Message-----
> From: linuxppc-embedded-bounces+rwood=ics-ltd.com at ozlabs.org
> [mailto:linuxppc-embedded-bounces+rwood=ics-ltd.com at ozlabs.org] On
> Behalf Of Robert Woodworth
> Sent: Wednesday, September 05, 2007 2:42 PM
> To: linuxppc-embedded at ozlabs.org
> Subject: Xilinx FX60
> 
> After achieving complete success with my Linux kernel on the ML403, I've
> now started to build a kernel for my real target board with a
> Virtex4-FX60 (dual PPC cores)
> 
> Has anyone built a kernel for a dual core PPC Virtex?  I have found very
> little docs on how to architect software for the dual-core PPC's.  
> Will SMP Linux work on this platform?  What would the bus setup be?
> 
> 
> 
> My kernel is partially booting, some of the time... I'm mystified by the
> situation.  One time, I get all the happy boot messages through the
> UARTLite port, then the next reboot it stops at "Now booting the kernel"
> I'm only getting about 10% successful boots......
> 
> 
> My EDK setup is as follows;  I've disconnected the second PPC from the
> PLB to have a single PPC system, 32MB DDR on PLB, TEMAC on PLB, UARTLite
> on OPB.
> 
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