external IRQ's

Scott Wood scottwood at freescale.com
Sat Aug 18 02:28:04 EST 2007

robert lazarski wrote:
> On 8/16/07, Scott Wood <scottwood at freescale.com> wrote:
>>robert lazarski wrote:
>>>Why <1d 2 1e 2 22 2> ? I can't seem to parse these numbers
>>They alternate between IRQ numbers and level/sense information, and the
>>IRQ numbers are the internal IRQ number plus 16.
> Thanks, The "internal IRQ number plus 16" part is the info I was
> lacking. However by 'internal IRQ' do you mean DMA? I just asked the
> hardware engineer and that's what he thought you may have meant.

No, I mean interrupts that come from on-chip devices, rather than 
external interrupt pins.

> So in '1d'  the first cell is the irq and the second cell is the sense
> level, how is the '1' calculated from 'internal IRQ number plus 16' .
> Thanks for you patience, I'm just not getting that part yet.

What do you mean, the '1'?

 From table 10-3 of the 8548 manual, the eTSEC1 transmit interrupt is 
internal interrupt 13, or 0xd.  Adding 16 gives 0x1d.

It's (apparently) level-triggered active-high, so the sense is 2, 
according to the table in booting-without-of.txt.

>>If, like the CDS board, you have level-triggered active-low phy
>>interrupts, then <0 1>, <1 1>, <2 1>, and <3 1>.  If not, then choose an
>>appropriate value for the second cell based on booting-without-of.txt.
> Kool, think I got this part. Do the 0-3 irq's in the mdio node
> influence in any way the ethernet nodes irq's - the <1d 2 1e 2 22 2>
> in this example ?



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