System crash on boot_e500.S on 2.4Kernel

[Andy Fleming]

On Aug 15, 2007, at 16:12, mike zheng wrote:

> Here is the PC value before the rfi:
>
> cds8458>halt
>            Target CPU:           : MPC85xx (e500v2 rev.1)
>            Target state            : halted
>            Debug entry cause  : instruction breakpoint
>            Current PC             : 0x0000015c
>            Current CR             : 0x24024022
>            Current MSR          : 0x00012100
>            Current LR              :0x00000148
>            Current CCSRBAR  :0x0_e000000
>
> After the rfi:
>
> #step timeout defected
> cds8458>halt
>            Target CPU:           : MPC85xx (e500v2 rev.1)
>            Target state            : halted
>            Debug entry cause  : COP halt
>            Current PC             : 0xfff81300
>            Current CR             : 0x24024022
>            Current MSR          : 0x00001000
>            Current LR              :0x00000148
>            Current CCSRBAR  :0x0_e000000

Ok, I'm sure your problem isn't that SRR0 isn't getting updated  
properly.  I suspect something is going wrong during the rfi.   
Possibly something in your TLBs.  However, what is happening is most  
likely that you have hit an exception, and SRR0 and SRR1 have been  
updated.  I'm a little confused by the addresses where you first  
invoke "halt".  It looks like you're in the middle of flash, which is  
an odd place in u-boot to be.

And if you look at your PC, it doesn't seem like you step.  It looks  
like something goes wrong with the debugging.  My suggestion is to  
check your TLB setup and your IVOR setup.  Find out if the IVORs are  
pointing at an exception at fff81300.

Andy