How do external irq's get mapped?

[Sergei Shtylyov]

Hello.

Charles Krinke wrote:
> As I understand it, the 8541 and 8555 have 12 external IRQ[0..11], 21
> internal interrupts, and 4 messaging interrupts.

> In looking at the MPC8555ERM.pdf file, which is my main resource, it
> looks like the internal interrupt numbers for the 1st TSEC are 19 for
> transmit and 20 for receive.

> A 'cat /proc/interrupts' shows the 1st TSEC transmit as 93 and the
> receive as 94, so I am puzzled how we get from 19 to 93 for the transmit
> and from 20 to 94 for the receive. Perhaps understanding this will help

   I'd suspect you also have CPM on this SoC (or have CONFIG_CPM* wrongly enabled?).

> me figure out what number to put into the pci_dev structure for external
> IRQ0.

   Could you post your /proc/interrupts?

 > Charles Krinke

WBR, Sergei