2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory controllers ( DSOCM and ISOCM )

[jozsef imrek]

On Tue, 24 Apr 2007, Mohammad Sadegh Sadri wrote:

> Then in mailing list I saw some where that AVNET mini-modules are using 
> a version of FX12 FPGA which has problem with PPC caches and as the 
> solution the caches should be off.

i think the relevant errata is this:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=20658
see solution 13.


as far as i understand the problem was caused by the plb2opb bridge
used in the design. the bridge was necessary because the plb_ddr
controller in earlier EDKs did not support the 16bit DDR memory
present on the avnet (earlier memec) minimodule, therefore you had to
use an opb_ddr controller.

however, the plb_ddr present in recent EDKs (ie plb_ddr v2.00.a)
_does_ support 16bit wide memory, therefore you do not need the
plb2opb bridge.

so as long as you are using the plb_ddr controller, and you are
disabling cache for other devices on the opb bus you should be
safe.



could someone with more authentic knowledge confirm this? anyone
from xilinx/avnet?



-- 
mazsi

----------------------------------------------------------------
strawberry fields forever!                       imrek at atomki.hu
----------------------------------------------------------------