Problems with SPI+I2S on MPC5200B

[Grant Likely]

John,

Kim Phillips pointed me in your direction.  I've got a 5200B based
platform w/ two AIC26 codecs attached to PSC2 and PSC3 in I2S modes,
and both are also connected to the SPI pins in the PSC3 pin group.
Linux is running on the board.

In the early development of this board, we had some problems with the
MPC5200 SPI device, and so implemented a gpio bitbanging driver
instead just to get things working, and we've got an ALSA driver that
works with both codecs.

Of course, the bitbanged SPI driver is sub-optimal so dug back into
the SPI device and put together a working MPC5200 SPI device driver.
For Codec #1 on PSC2, this setup works perfectly.  However, Codec #2
no longer works.  An application can connect to the ALSA device, but
no audio data gets transfered in/out of the MPC5200.  If I switch back
to bitbanging mode, everything works again.

Things I've verified:
1. SPI read/write to the Codec is correct.  All the settings are
identical between the working codec and the non-working one
2. Both codecs are correctly generating I2S BitClk and Frame signals
3. On the working codec, PSC2+0x2210 reports 0x80000000, detected SYNC
4. On the non-working codec, PSC3+0x2410 reports 0x00000000, no detected SYNC
5. If I 'wrap' the spi transfers with modifications to port_config to
enable/disable SPI to the PSC3 pin group, then audio works again.
(However, this is not a viable solution because we have a lot of
transfers across the SPI bus).

Here is some of the relevant data:

Setup of port_config

	printk("old port_config=%.8x\n", val);
	/* 48Mhz internal, pin is GPIO */
	val &= ~0x00800000;

	/* USB port - Differential mode - USB1 only */
	/* Commented out until Atmel has proper firmware loaded
	val &= ~0x00007000;
	val |=  0x00001000;
	*/

	/* CODEC2 + GPIO on PSC2 */
	val &= ~0x00000070;
	val |= 0x00000060;

#if !defined(CONFIG_MPC5200_SPI_BITBANG)
	/* SPI+CODEC3 pins on PSC3 */
	val &= ~0x00000F00;
	val |= 0x00000F00; /* CODEC3 + SPI */
#else
	/* GPIO+CODEC3 pins on PSC3 */
	val &= ~0x00000F00;
	val |= 0x00000600;
#endif

	/* Commit port config */
	out_be32(&gpio->port_config, val);
	printk("new port_config=%.8x\n", val);

'Wrapper' code on SPI driver just to get things working (Called at the
start and end of an SPI transfer)

void port_config_enable_spi(void)
{
	u32 val;
	udelay(1);
	val = in_be32(&gpio->port_config);
	val |= 0x00000F00; /* CODEC3 + SPI */
	out_be32(&gpio->port_config, val);
	udelay(1);
}

void port_config_disable_spi(void)
{
	u32 val;
	udelay(1);
	val = in_be32(&gpio->port_config);
	val &= ~0x00000F00;
	val |= 0x00000600;
	out_be32(&gpio->port_config, val);
	udelay(1);
}


I2S interface:
AIC26 is master, MPC5200 is slave
bitclk generated by AIC26

SPI interface
SS controlled by a CPLD
MPC5200 is master
SPI transfers are confirmed working for both bitbanging and SPI device drivers.

Register dump for PSC2 (working) and PSC3 (not working):
>md 0xf0002200
f0002200 : 07000000 1f000000 00000000 05165dd3  ..............].
f0002210 : 80000000 1b000000 00000000 00000000  ................
f0002220 : 00000000 00000000 00000000 00000000  ................
f0002230 : 00000000 bc000000 00000000 00000000  ................
f0002240 : 2f600000 00000000 00000000 36000000  /`..........6...
f0002250 : 00000000 00000000 02000000 00000000  ................
f0002260 : 05165dd3 00060000 04200000 00000100  ..]...... ......
f0002270 : 00000010 00000010 00000000 00000000  ................
f0002280 : 00000000 00230000 07200000 00000100  .....#... ......
f0002290 : 000001b0 000001b0 000001b0 000001b0  ................
f00022a0 : 00000000 00000000 00000000 00000000  ................
f00022b0 : 00000000 00000000 00000000 00000000  ................
f00022c0 : 00000000 00000000 00000000 00000000  ................
f00022d0 : 00000000 00000000 00000000 00000000  ................
f00022e0 : 00000000 00000000 00000000 00000000  ................
f00022f0 : 00000000 00000000 00000000 00000000  ................

>md 0xf0002400
f0002400 : 07000000 00000000 00000000 00000000  ................
f0002410 : 00000000 00000000 00000000 00000000  ................
f0002420 : 00000000 00000000 00000000 00000000  ................
f0002430 : 00000000 fc000000 00000000 00000000  ................
f0002440 : 2f600000 00000000 00000000 36000000  /`..........6...
f0002450 : 00000000 00000000 00000000 01e80000  ................
f0002460 : 00000000 00210000 04200000 00000100  .....!... ......
f0002470 : 00000000 00000000 00000000 00000000  ................
f0002480 : 10010000 00000000 07200000 00000100  ......... ......
f0002490 : 0000000c 000001f0 00000000 00000000  ................
f00024a0 : 00000000 00000000 00000000 00000000  ................
f00024b0 : 00000000 00000000 00000000 00000000  ................
f00024c0 : 00000000 00000000 00000000 00000000  ................
f00024d0 : 00000000 00000000 00000000 00000000  ................
f00024e0 : 00000000 00000000 00000000 00000000  ................
f00024f0 : 00000000 00000000 00000000 00000000  ................


-- 
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
grant.likely at secretlab.ca
(403) 399-0195