Some questions about the Xilinx Temac driver.

[Michael Galassi]

If you use the latest xilinx ISE/EDK/IP update and let it overlay your
mvl source tree with it's files it shouldn't take you more than a few
hours to patch things up to where you can compile a kernel which will
work on the 3.00b IP.  The PHY support is useless but you can work
around that easily enough.  I've not tried to get any of that working
with a semi-current kernel so if you're not using mvl's flavor of 2.6.10
you may run into other issues.

-michael

>Dear Andrei,
>I have some questions about your xilinx Temac driver. If possible, please 
>give me a hand on such confusing problems. 
>
>1. I am using the driver from 
>http://source.mvista.com/~ank/paulus-powerpc/20060309/, and the IP cores of 
>plb_temac and hard_temac whose hardware versions are 2.00a and 1.00a 
>specifically. I know the newest versions of those hardwares are 3.00a and 
>3.00a. Is your driver support the 3.00a version hardware? Also, is the 
>driver from http://source.mvista.com/~ank/paulus-powerpc/20060309/ the 
>latest one for Xilinx Temac? If you have some updated version, please tell 
>me the address. 
>
>2. Is that driver from the above address able to support SGDMA? In fact, I 
>am testing the throughput of the Temac enet by my own little program which 
>is very simple. In the program running on the board, the pseudo code looks 
>just like this:
>     for(;;){
>           select();
>           if(FD_ISSET()){
>                 recvfrom();
>           }
>           
>           sendto();
>     }
>
>The program is just to receive packets from a pc and then transfer them 
>back. But in this condition, the embedded PowerPC CPU is easily used by 
>100&. So I suspect that maybe the DMA is not running properly. Could you 
>please say something about the DMA in your driver? 
>
>Thanks a lot for your telling.
>
>Regards
>Ming
>
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