Performance on PowerQuicc8280 linux based

[Dan Malek]

On Nov 15, 2006, at 11:21 AM, Jeff Mock wrote:

> I'm no big help, but the problem might be TLB related instead of cache
> related.  The performance of embedded PPCs with small TLBs requiring
> software assist for TLB misses can be performance sensitive to TLB  
> misses.

The 82xx is fully cache coherent and has BATs for
mapping the kernel space.  This is not a PPC with
a small TLB, but rather one of the most efficient.
The TLBs are not an issue,  and I doubt the caches
are as well.

I don't know what kind of test is used to measure this
performance, but the first thing you must always scrutinize
are your testing methods and procedures.  Just using
a user application to measure network performance
enables a large number of variables that must be
properly understood and controlled.  Some other
thread could have switched in and stolen CPU cycles,
you could have some sampling rate and time
measurement hysteresis due to buffering,
you need to find and control such things.

Can you "undo" the changes and get the old
results?  That's the first thing I would verify,
and then verify the results are repeatable.
If that's the case, I'd carefully try to understand
what this "unrelated" change really affects
in terms of using CPU cycles.

Thanks.

	-- Dan