Setting I&D cache enable in the same mtspr instruction

[Assaf Hoffman]

Attached.
Thanks.

-----Original Message-----
From: Mark A. Greer [mailto:mgreer at mvista.com] 
Sent: Monday, May 15, 2006 10:00 PM
To: Assaf Hoffman
Cc: linuxppc-embedded at ozlabs.org; Rita Shtern; Ronen Shitrit
Subject: Re: Setting I&D cache enable in the same mtspr instruction

On Mon, May 08, 2006 at 01:39:13PM +0300, Assaf Hoffman wrote:
> Hi,
> I think the implementation of setup_common_caches() in file
> cpu_setup_6xx.S; not according to the spec as far as MPC74xx concerns.
> Looking in the spec (MPC7450 RISC Microprocessor Family Reference
> Manual, MPC7450UM Rev. 5 1/2005) section 3.4.1.5 L1 Instruction and
Data
> Cache Flash Invalidation it says: 
> "Note that HID0[ICFI] and HID0[DCFI] must not both be set with the
same
> mtspr instruction, due to the synchronization requirements described
in
> Section 2.4.2.4.1, "Context Synchronization."
> But in the code those two do set together.
> Also, the same section says: 
> "An isync must precede the setting of the HID0[ICFI] in order for the
> setting to take effect."
> But in the code, only 'sync' can be found.
> 
> /* Enable caches for 603's, 604, 750 & 7400 */
> setup_common_caches:
> 	mfspr	r11,SPRN_HID0
> 	andi.	r0,r11,HID0_DCE
> 	ori	r11,r11,HID0_ICE|HID0_DCE
> 	ori	r8,r11,HID0_ICFI
> 	bne	1f			/* don't invalidate the D-cache
> */
> 	ori	r8,r8,HID0_DCI		/* unless it wasn't enabled */
> 1:	sync
> 	mtspr	SPRN_HID0,r8		/* enable and invalidate caches
> */ 
>       ^^^^^^^^^^^^^^^^^^^ Here we set both ICFI and DCFI in the same
> mtspr instruction. Also, no isync before setting ICFI.
> 	sync
> 	mtspr	SPRN_HID0,r11		/* enable caches */
> 	sync
> 	isync
> 	blr
> 
> Please advice.
> Thanks.

Yep, looks like a bug.  How about a patch?  :)

Mark
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