MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Zhang Wei-r63237]

Hi, 

Please see inline comments.

Best Regards,
Zhang Wei

> -----Original Message-----
> From: 
> linuxppc-embedded-bounces+wei.zhang=freescale.com at ozlabs.org 
> [mailto:linuxppc-embedded-bounces+wei.zhang=freescale.com at ozla
> bs.org] On Behalf Of Florian Boelstler
> Sent: Monday, June 26, 2006 6:48 PM
> To: linuxppc-embedded at ozlabs.org
> Subject: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
> 
> Hi,
> 
> I am currently working on a MPC8548-based development system.
> Linux kernel version is 2.6.11 with patches delivered from 
> Freescale (BSP MPC8548CDS 02/24/2006).
> 
> Kernel configuration contains a warning message for CONFIG_PEX:
> "This requires hardware modification to work correctly if 
> your CPU version < 2.0 and will break the PCI bus. [...]"
> 
> I was wondering whether enabling PCIe makes PCI bus 
> functionality unusable at all (including kernel functionality 
> for detecting devices behind a transparent PCI-to-PCI bridge).

The interrupts polarity of MPC8548 PCIe controller is reversed to PCI. That's an errata of MPC8548.
So you must rework to fix them. You can find the detail from user manual of bsp.

> 
> Our setup connects a transparent PLX8516 PCI-to-PCI bridge to 
> the PCIe port of the MPC8548 daughter board. Behind that 
> bridge is another PCIe capable device.
> MPC8548 is configured to run as PCIe host mode.
> 
> When trying to lookup the PCIe devices using lspci I can only 
> see the PPC itself and the bridge.
> However I cannot see the device(s) behind the bridge.

Yes, that's also an errata to MPC8548 PCIe controller.
Trying to apply below patch code:

diff -u -r1.1.1.2.2.3 ppc85xx_setup.c
--- arch/ppc/syslib/ppc85xx_setup.c	7 Apr 2006 08:57:50 -0000	1.1.1.2.2.3
+++ arch/ppc/syslib/ppc85xx_setup.c	27 Jun 2006 02:45:54 -0000
@@ -256,6 +256,7 @@
 {
 	volatile struct ccsr_pex *pex;
 	unsigned short temps;
+	unsigned int pribus;
 	bd_t *binfo = (bd_t *) __res;
 
 	pex = ioremap(binfo->bi_immr_base + MPC85xx_PEX_OFFSET,
@@ -265,6 +266,11 @@
 	temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+	/* PCIE Bus, Fix the MPC8548 host bridge's location to bus 0xFF. */
+	early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &pribus);
+	pribus = (pribus & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+	early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, pribus);
 
 	/* Disable all windows (except powar0 since its ignored) */
 	pex->pexowar1 = 0; 
> 
> Is there another method for detecting PCI(e) devices?
> Is "BSP MPC8548CDS 02/24/2006" the latest version 
> corresponding to that hardware?

Yes, it's the last version.

> 
> Thanks in advance,
> 
>    Florian
> 
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