[26-devel] v2.6 performance slowdown on MPC8xx: Measuring TLB cache misses

[Dan Malek]

On May 7, 2005, at 2:10 PM, Joakim Tjernlund wrote:

> Not completly sure that this is correct. There are a few:
> 	addi	r10, r10, 0x0100
>  	mtspr	SPRN_MD_CTR, r10
> later on which will "overflow" 0x1f00 into 0x2000 etc.

Oh right, I forgot I did that.  I explicitly set the tlb index before
each write.  Sorry, I thought it was due to more bits of index
in the 885.

So, I guess what was there should have worked.

OK, so the reason TLB pinning doesn't work is a tlbie() can
evict the pinned entry.  That stupid code in the cpm reset
will throw them out, plus anything else that would do a
tlbie() of a kernel address within the pinned space (like
the update_mmu_cache() hack).  We have to fix those,
and look for any others where that may happen.

Thanks.


	-- Dan