440GX interrupt

Barbier, Renaud (GE Infrastructure) Renaud.Barbier at ge.com
Fri Feb 18 08:50:27 EST 2005

I have a question regarding interrupt and irq locking.
I derived  (or copied from somehwere)a library (linux 2.4.26) for the 440GX from ppc4xx_pic.c to take care of the last interrupt register (UIC2).
This a newbie question regarding get_irq/spin_lock
here is get_irq:
     bits = mfdcr(DCRN_UIC_MSR(UICBASE));
     if ((bits & 0x40000000) == 0x40000000)
        bits = mfdcr(DCRN_UIC_MSR(UIC0));
        irq = ( ffs(bits));
        irq = 32-irq;

my question is what guarantee that the code is executed atomically?

The reason I asked is that we have a driver that did the following in the ioctl call:

	/* do something */

as you noticed there is not any spin_lock.
Sometimes, this leads  get_irq to see UICBASE indicating an irq in UIC0 and
UIC0_MSR to return 0. hence you get irq 32 (MAL_SERR) and an infinite loop.

My current fix is to use irqsave/irqrestore in the driver which I think is the correct way to do (but I may be wrong please help).

However, I have a colleague (here is the human problem of my questions: him or me is the problem) that insists that I should do something in get_irq to have atomic execution.

can you share your view about get_irq and spin_lock?

If it is not the correct place to ask this question, let me know where to send it.

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