mpc8248 SEC -- interrupt handler 'is' invoked

[Vikas Aggarwal]

Hi Kim,
  While browsing the SIU came across TESCR1(0x10040) & TESTCR2(0x10044). I
dumped it during module_init (00000000::00000000)  and also in the ISR
after RNG was submitted to SEC core, this time I got
(0x814a0000::00000000).

TESCR1 after RNG descriptor submitted and SEC-ISR invoked=0x814a0000
bit 0 set -- 60x bus monitor timeout
bit 7-9=  101 --- SEC transaction
bit 11-15=01010 -- TT -- Single-beat-read or burst.

Now looking more into SIU -- SIU-BCR(bus Configuration register=0x10024)
has EBM bit , i set that. Did'nt make any difference. :(

I want to ask -- To make SEC 1.0 as master do i have to do several other
modifications to the SIU configurations so that 60x bus mode is enabled
for internal master. Like PPC_ACR(0x10028)  has 4-7 bits as PRKM-parking
master and PPC_ACR=0100 stands for SEC engine.

-vikas


> On Tue, 9 Aug 2005 16:52:04 -0400 (EDT)
> "Vikas Aggarwal" <va824363 at albany.edu> wrote:
>
>> The address returned by kmalloc=0x009ffc5c  is 4 byte aligned.
>> Are u advicing that dma_map_single() should return 8 byte aligned ,
>> becuase thats what gets written into the Data-Paclet_descriptor later.
>>
> I wouldn't worry about alignment as much as the register write trace and
> checking the System Interface Unit and individual eu status registers.
>
> --
> Kim
>