MPC5200 Cache coherency with BestComm issue

[Sylvain Munaut]

Hi Roger

> By experimenting I have found that the BestComm and FEC work without
>the cache flush provided CPU_FTR_MAYBE_CAN_NAP is removed from the
>cputable (nap disables snooping) and that CPU_FTR_NEED_COHERENT is
>added to the cputable (turns on "M" bit in BAT/PTE so that the XLB has
>a chance of seeing a global transaction).
>  
>
Thanks for the info.

The nap thing was indeed obvious ... The proper way to deactivate it 
would be in lite5200.c
I added the powersave_nap = 1; as an example on how to allow it to nap. 
I'll probably
comment it out by default with a note.

For the CPU_FTR_NEED_COHERENT, are you sure it's required ?
 From my understanding of the G2Core manual, the M bit must be set if 
you want the G2Core
to assert the global signal when it access memory. Here, we don't care 
since only
the G2Core is snooping on the bus. So that should not be required ...


    Sylvain