MPC5200 Cache coherency with BestComm issue

[roger blofeld]

Sylvain,
 By experimenting I have found that the BestComm and FEC work without
the cache flush provided CPU_FTR_MAYBE_CAN_NAP is removed from the
cputable (nap disables snooping) and that CPU_FTR_NEED_COHERENT is
added to the cputable (turns on "M" bit in BAT/PTE so that the XLB has
a chance of seeing a global transaction).

I don't know if that will work for all G2_LE cores, but it seems
required for the 5200.
-rb

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