Bug in new IBM 4xx on-chip Ethernet drivers?

[llandre]

Hi Eugenene,

I can confirm your experience. As phy we use the STE100P from ST. I've
never seen it to
fail with MII clock frequency set to 3.3MHz. Anyway I think that, for
production,
it should be set to 2.5MHz as requested by the datasheet.


>On Wed, Mar 03, 2004 at 10:48:00AM +0100, llandre wrote:
> > I'm working with a custom 405EP-based board. So far I used the kernel
> 2.4.20
> > and now I'm moving to the 2.4.23. I realized that the on-chip Ethernet MAC
> > driver
> > changed.
> > I have a question about the function emac_phy_read in ibm_ocp_enet.c file.
> > In my understanding the following snippet is not correct
> >
> >         /* Clear the speed bits and make a read request to the PHY */
> >         stacr = ((EMAC_STACR_READ | (reg & 0x1f)) &
> ~EMAC_STACR_CLK_100MHZ);
> >         stacr |= ((mii_id & 0x1F) << 5);
> >
> > because it assumes the OPB clock frequency is 50MHz. If it differs,
> > the MII clock frequency generated by the Ethernet controller is erroneous.
> > For example, with OPB frequency = 66MHz, the MII clock frequency is set
> > to 3.3MHz (this should be 2.5MHz).
>
>Although you are rigth that this code needs fixing, my experience with
>different 4xx hardware running with different OPB clock speed showed
>that even incorrect setting doesn't affect MII operation.
>
>And to be fair, all previous EMAC drivers had the same bug :).
>
>Eugene.




llandre


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