Master receiver issue with freescale i2c-mpc driver/2.4?

[Stefan Nickl]

Found another strangeness with this driver:

If I get I2C right (I might be severely misguided here),
when watching a master receive data from a slave transmitter,
all the incoming data will be ACKed by the master, except
for the last data byte, where SDA is supposed to be high during
the 9th cycle.
What I'm referring to is this part of the ST M4181 RTC manual (p9):

-------------------------------------------------------
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during
the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal
an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
-------------------------------------------------------

But what I saw was a low SDA during *all* the ACK cycles,
until I did what's in the patch.
It's working, plus what I see on the LA looks much better now.

PS: Is Kumar on holiday or am I just getting on his nerves? ;)

PPS: If anyone's interested in drivers for the Microchip
     EEPROMs with 2 byte addressing and that ST RTC, don't
     hesitate to ask.

--
Stefan Nickl
Kontron Modular Computers

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