82xx and cache coherency between CPM and CPU

[Peter Krogsgaard]

Hi,

I have been browsing through the driver code for the MPC8260 from the
cvs
repository at denx.de (linuxppc_2_4_devel).

One thing that makes me wonder is why some of the drivers (i2c, spi)
calls
flush_dcache_range and friends instead of setting the gobal access bit
(GBL)
in the rfcr/tfcr registers for the device?

As I read the docs the 82xx are cache coherent between the CPU and the
CPM so
the GBL bit should do the trick.

Am I missing something obvious here ?


Best regards

Peter Krogsgaard
Focon Electronic Systems A/S


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