82xx and cache coherency between CPM and CPU

Peter Krogsgaard PKA at Focon.dk
Tue Aug 10 00:35:45 EST 2004


I have been browsing through the driver code for the MPC8260 from the
repository at denx.de (linuxppc_2_4_devel).

One thing that makes me wonder is why some of the drivers (i2c, spi)
flush_dcache_range and friends instead of setting the gobal access bit
in the rfcr/tfcr registers for the device?

As I read the docs the 82xx are cache coherent between the CPU and the
CPM so
the GBL bit should do the trick.

Am I missing something obvious here ?

Best regards

Peter Krogsgaard
Focon Electronic Systems A/S

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