Caching in the MPC107

[Adrian Cox]

On Tue, 2002-09-10 at 18:03, Mark A. Greer wrote:

> I think I understand what you're saying.  The biggest question that comes to
> my mind, though, is whether this is a problem on many of the other
> hostbridges?  Most of the newer bridges will buffer a cacheline or two.  Is
> this a wider issue than just the 107?

I haven't looked this closely at any other bridges. Many bridges have
buffers to prefetch data during a PCI burst read, but empty the buffers
when the PCI transaction ends. The clever feature of the MPC107 is that
it holds the data to satisfy a later read, and it snoops the 60x bus for
cycles that affect its cache.

- Adrian


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