very minor 405GP and 405GPr PCI difference

[Todd Poynor]

David Gibson wrote (regarding Rainier PMM1 bios_fixup in MVL):

> Well, it may be in a different place, but it looks like it has the
> same problem.  It is still establishing a PCI window at PLB address
> 0x80000000, which is the same address used for the PMM0 window - or is
> that also different in the MV kernel?
>
> I'd be trying to work out what that mapping's actually for, first.  I
> still can't see how it can possibly work - if there are overlapping
> PMM windows, what actually happens to accesses in that (PLB) range?

Yes, it looks like MVL only sets up the one window using PMM1... we've
started an effort to have the Rainier-knowedgeable folks get the code
sync'ed up with the community and this should happen soon.


--
Todd


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