dcache and 8260_io/fcc_enet.c

[Joakim Tjernlund]

Crap, disregard my previous mail.

The 8260 CPM is aware of the CPU dcache and therefor you don't need to flush
the data before handing the buffer over to the CPM. The CPM 8xx family CPU
has no understanding of the CPU caches and needs an explicit flush.

  Jocke
>
> >
> > I noticed that fcc_enet_start_xmit() does not flush the transmit data before
> > setting up the transmit buffer descriptor. I get the impression that this is
> > not necessary. But I don't understand why. I have spent the morning looking
> > through code and Motorola docs and am non the wiser.
>
> That's because the 8260 CPU understand the CPU caches and, while the 8xx does not
> and therefore needs a flush_dcache_range().
>
>     Jocke
>
> >
> > Thanks
> > Dean
>
>
>
>


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