question regarding organization of the pte hash table

[Neil Horman]

Hello all-
	If anyone has a free moment, I'm looking for education regarding the
organization and manipulation of the hash table which stores pte that are not
listed in the TLB or software tables used by the MMU.  From what I read
regarding the use of the PPC860 MMU (my processor in question), multiple page
tables/directories are interleaved through the use of the ASID/CASID identifiers
which must match for a MMU translation to be successful.  If I understand it
correctly the hash table stores pte's which have been victimized from the MMU
TLB and/or software tables due to another memory context (CASID) using that same
virtual address.  If that is correct, then I would like to better understand the
hashing functions which the hash table uses to store ptes with identical virtual
address and different CASID's.  Also, if my previous thinking is correct, the
hash table in question must be limited in the number of CASID's which it
supports, and consequently, the number of processes which can be run at any one
time.  How is that limit determined?.  If anyone knows of any documentation on
the subject, or knows where in the source tree I can get a better understanding
of the hash tables function I'd certainly appreciate it.  I've tried to glean
something from hash_page down in hashtable.S and I'm really quite lost.  Thanks
all!
Neil

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