dcache BUG()

[Dan Malek]

Eli Chen wrote:

> >From the PPC manual:
> "Because the hardware doesn't compare reservation address when executing the
> stwcx.

F**K...that's what I was looking for.  What manual is that in?
Everything I have handy (older UISA books), state the granularity
is implementation dependent.  I couldn't find any 4xx manual that
stated the granularity of the reservation.  I thought 6xx/7xx at
least checked cache line granularity in addition to a single
reservation bit.

Gabriel is right................


	-- Dan

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