Using zImage.initrd

[Dan Malek]

Daniel Wu wrote:


> .... The loader is
> copied to 0x600000 and execute from there ( I've reserved 4M for the boot +
> zImage + initrd). Will this be a problem?

That isn't necessary.  The code in the mbxboot directory takes care
of reserving space.  It assumes the loader is copied into _lower_
memory from the load point.  All of these build procedures in the
generic sources work very nicely and you shouldn't have to change
anything.



> The CPU is 860T (XPC860TZP50B3). The caches are enabled as far as I can tell
> from the code.

So, have you run any diagnostics to make sure your UPM programming
is working correctly?  When Linux comes to life with caches, MMU,
and the CPM running, it creates worst case memory cycles that are
very difficult to duplicate with diagnostic programs.  Any little
memory timing problem will show up here.  I would suggest completely
disabling the cache (I guess I should add a kernel configuration
for this).  See the attachment.

> > What is the rest of this backtrace?
> >
>
> C00FF71B buf
> C00B8474 extract_entropy
> C00B8648 get random_bytes
> C00FA2B4 init_elf_binfmt
> C00F7774 start_kernel
> C000221C start_here

Oh wow.....If this is really where the code is running, something
very fundamental is broken in the hardware because there should have
been lots more printed out on the console.  You are still running in
very generic kernel functions that work on all architectures.


	-- Dan
-------------- next part --------------


Change the code that looks like this:


	lis	r8, IDC_INVALL at h
	mtspr	IC_CST, r8
	mtspr	DC_CST, r8
	lis	r8, IDC_ENABLE at h
	mtspr	IC_CST, r8
#ifdef CONFIG_8xx_COPYBACK
	mtspr	DC_CST, r8
#else
	/* For a debug option, I left this here to easily enable
	 * the write through cache mode
	 */
	lis	r8, DC_SFWT at h
	mtspr	DC_CST, r8
	lis	r8, IDC_ENABLE at h
	mtspr	DC_CST, r8
#endif

/* We now have the lower 8 Meg mapped into TLB entries, and the caches
 * ready to work.
 */
#endif /* CONFIG_8xx */
	b	turn_on_mmu



To look like this:


	lis	r8, IDC_INVALL at h
	mtspr	IC_CST, r8
	mtspr	DC_CST, r8
#if 0
	lis	r8, IDC_ENABLE at h
	mtspr	IC_CST, r8
#ifdef CONFIG_8xx_COPYBACK
	mtspr	DC_CST, r8
#else
	/* For a debug option, I left this here to easily enable
	 * the write through cache mode
	 */
	lis	r8, DC_SFWT at h
	mtspr	DC_CST, r8
	lis	r8, IDC_ENABLE at h
	mtspr	DC_CST, r8
#endif
#else
	lis	r8, IDC_DISABLE at h
	mtspr	IC_CST, r8
	mtspr	DC_CST, r8
#endif