[PATCH RFC 4/4] powerpc/radix: Add support for microwatt's PRTBL SPR

[Nicholas Piggin]

Excerpts from Paul Mackerras's message of May 9, 2020 3:04 pm:
> Microwatt currently doesn't implement hypervisor mode and therefore
> doesn't implement the partition table.  It does implement the process
> table and radix page table walks.
> 
> This adds code to write the base address of the process table to the
> PRTBL SPR, which has been assigned SPR 720 for now, as that is in the
> range of SPR numbers assigned for experimental use.  PRTBL is only
> written when we have neither the FW_FEATURE_LPAR feature nor the
> CPU_FTR_HVMODE feature.

What do you think about adding a FW_FEATURE and/or CPU_FTR for
microwatt?

No big deal now, but I'm sure you'll be adding other things.

Thanks,
Nick

> 
> Signed-off-by: Paul Mackerras <paulus at ozlabs.org>
> ---
>  arch/powerpc/include/asm/reg.h           |  1 +
>  arch/powerpc/mm/book3s64/radix_pgtable.c | 13 +++++++++----
>  2 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 1aa46dff0957..6ea3fc42740d 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -721,6 +721,7 @@
>  #endif
>  #define SPRN_TIR	0x1BE	/* Thread Identification Register */
>  #define SPRN_PTCR	0x1D0	/* Partition table control Register */
> +#define SPRN_PRTBL	0x2D0	/* Process table pointer */
>  #define SPRN_PSPB	0x09F	/* Problem State Priority Boost reg */
>  #define SPRN_PTEHI	0x3D5	/* 981 7450 PTE HI word (S/W TLB load) */
>  #define SPRN_PTELO	0x3D6	/* 982 7450 PTE LO word (S/W TLB load) */
> diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c
> index dd1bea45325c..2e6a376c9d82 100644
> --- a/arch/powerpc/mm/book3s64/radix_pgtable.c
> +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c
> @@ -600,10 +600,15 @@ void __init radix__early_init_mmu(void)
>  	radix_init_pgtable();
>  
>  	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
> -		lpcr = mfspr(SPRN_LPCR);
> -		mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> -		radix_init_partition_table();
> -		radix_init_amor();
> +		if (cpu_has_feature(CPU_FTR_HVMODE)) {
> +			lpcr = mfspr(SPRN_LPCR);
> +			mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> +			radix_init_partition_table();
> +			radix_init_amor();
> +		} else {
> +			mtspr(SPRN_PRTBL, (__pa(process_tb) |
> +					   (PRTB_SIZE_SHIFT - 12)));
> +		}
>  	} else {
>  		radix_init_pseries();
>  	}
> -- 
> 2.25.3
> 
>