[PATCH] cxl: Prevent IRQ storm

[Andrew Donnellan]

On 27/04/17 11:09, Alastair D'Silva wrote:
>> Patch looks good, thanks!
>> It doesn't apply cleanly on the 'next' tree due to the capi2
>> patchset
>> though, so you should probably rebase on that tree. The bits have
>> changed a bit on PSL9, but the approach still works (error type
>> reported
>> in the first byte, and the corresponding masking bits are still
>> right-shifted by 32).
>>
>
> Hmm, both you & the documentation say 8 bits, but the code suggests 9:
> #define CXL_PSL_SERR_An_afuto	(1ull << (63-0))
> #define CXL_PSL_SERR_An_afudis	(1ull << (63-1))
> #define CXL_PSL_SERR_An_afuov	(1ull << (63-2))
> #define CXL_PSL_SERR_An_badsrc	(1ull << (63-3))
> #define CXL_PSL_SERR_An_badctx	(1ull << (63-4))
> #define CXL_PSL_SERR_An_llcmdis	(1ull << (63-5))
> #define CXL_PSL_SERR_An_llcmdto	(1ull << (63-6))
> #define CXL_PSL_SERR_An_afupar	(1ull << (63-7))
> #define CXL_PSL_SERR_An_afudup	(1ull << (63-8))
>
> Referenced from irq.c:cxl_afu_decode_psl_serr()
>
> Thoughts?

The latest version of the (IBM internal) PSL8 workbook which I happen to 
have at hand lists bit 8 as "Reserved" in the bitfield diagram, but 
lists it as "afudup" in the description underneath, so I think it's safe 
to say it's the first 9 bits.

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan at au1.ibm.com  IBM Australia Limited