[PATCH] cxl: Prevent IRQ storm

Alastair D'Silva alastair at au1.ibm.com
Thu Apr 27 11:09:11 AEST 2017


On Wed, 2017-04-26 at 11:23 +0200, Frederic Barrat wrote:
> 
> Le 26/04/2017 à 08:40, Alastair D'Silva a écrit :
> > From: Alastair D'Silva <alastair at d-silva.org>
> > 
> > In some situations, a faulty AFU slice may create an interrupt
> > storm,
> > rendering the machine unusable. Since these interrupts are
> > informational
> > only, present the interrupt once, then mask it off to prevent it
> > from
> > being retriggered until the card is reset.
> > 
> > Signed-off-by: Alastair D'Silva <alastair at d-silva.org>
> > ---
> 
> Patch looks good, thanks!
> It doesn't apply cleanly on the 'next' tree due to the capi2
> patchset 
> though, so you should probably rebase on that tree. The bits have 
> changed a bit on PSL9, but the approach still works (error type
> reported 
> in the first byte, and the corresponding masking bits are still 
> right-shifted by 32).
> 

Hmm, both you & the documentation say 8 bits, but the code suggests 9:
#define CXL_PSL_SERR_An_afuto	(1ull << (63-0))
#define CXL_PSL_SERR_An_afudis	(1ull << (63-1))
#define CXL_PSL_SERR_An_afuov	(1ull << (63-2))
#define CXL_PSL_SERR_An_badsrc	(1ull << (63-3))
#define CXL_PSL_SERR_An_badctx	(1ull << (63-4))
#define CXL_PSL_SERR_An_llcmdis	(1ull << (63-5))
#define CXL_PSL_SERR_An_llcmdto	(1ull << (63-6))
#define CXL_PSL_SERR_An_afupar	(1ull << (63-7))
#define CXL_PSL_SERR_An_afudup	(1ull << (63-8))

Referenced from irq.c:cxl_afu_decode_psl_serr()

Thoughts?

-- 
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819



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