[v5,1/7] QE: Add IC, SI and SIRAM document to device tree bindings.

[Scott Wood]

On Wed, Mar 09, 2016 at 09:21:28AM +0800, Zhao Qiang wrote:
> Add IC, SI and SIRAM document of QE to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> 
> Signed-off-by: Zhao Qiang <qiang.zhao at nxp.com>
> Acked-by: Rob Herring <robh at kernel.org>
> ---
> changes for v2
> 	- Add interrupt-controller in Required properties
> 	- delete address-cells and size-cells for qe-si and qe-siram
> Changes for v3
> 	- Add SoC specific caompatible strings to qe-si and qe-siram
> Changes for v4
> 	- NA 
> Changes for v5
> 	- NA 
> 
>  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50 ++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> index 4f89302..7ab21cb 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> @@ -69,6 +69,56 @@ Example:
>  	};
>       };
>  
> +* Interrupt Controller (IC)
> +
> +Required properties:
> +- compatible : should be "fsl,qe-ic".
> +- reg : Address range of IC register set.
> +- interrupts : interrupts generated by the device.
> +- interrupt-controller : this device is a interrupt controller.
> +
> +Example:
> +
> +	qeic: interrupt-controller at 80 {
> +		interrupt-controller;
> +		compatible = "fsl,qe-ic";
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +		reg = <0x80 0x80>;
> +		interrupts = <95 2 0 0  94 2 0 0>; //high:79 low:78
> +	};

Why is the information about which interrupt is "high" and which is
"low" in a comment in the example, rather than in the definition of the
interrupts property?

> +* Serial Interface Block (SI)
> +
> +The SI manages the routing of eight TDM lines to the QE block serial drivers
> +, the MCC and the UCCs, for receive and transmit.
> +
> +Required properties:
> +- compatible : should be "fsl,t1040-qe-si".
> +- reg : Address range of SI register set.

Is t1040 the only chip that has or will ever have this?

-Scott