[PATCH v2 2/2] powerpc32: optimise csum_partial() loop

Scott Wood scottwood at freescale.com
Fri Aug 7 08:45:45 AEST 2015

On Wed, 2015-08-05 at 23:39 -0500, Segher Boessenkool wrote:
> On Wed, Aug 05, 2015 at 09:31:41PM -0500, Scott Wood wrote:
> > On Wed, 2015-08-05 at 19:30 -0500, Segher Boessenkool wrote:
> > > On Wed, Aug 05, 2015 at 03:29:35PM +0200, Christophe Leroy wrote:
> > > > On the 8xx, load latency is 2 cycles and taking branches also takes
> > > > 2 cycles. So let's unroll the loop.
> > > 
> > > This is not true for most other 32-bit PowerPC; this patch makes
> > > performance worse on e.g. 6xx/7xx/7xxx.  Let's not!
> > 
> > Chips with a load latency greater than 2 cycles should also benefit from 
> > the 
> > unrolling.  Have you benchmarked this somewhere and seen it reduce 
> > performance?  Do you know of any 32-bit PPC chips with a load latency 
> > less 
> > than 2 cycles?
> The original loop was already optimal, as the comment said.

The comment says that bdnz has zero overhead.  That doesn't mean the adde 
won't stall waiting for the load result.

> The new code adds extra instructions and a mispredicted branch.

Outside the main loop.

>   You also might get less overlap between the loads and adde (I didn't check
> if there is any originally): those instructions are no longer
> interleaved.
> I think it is a stupid idea to optimise code for all 32-bit PowerPC
> CPUs based on solely what is best for a particularly simple, slow
> implementation; and that is what this patch is doing.

The simple and slow implementation is the one that needs optimizations the 

If this makes performance non-negligibly worse on other 32-bit chips, and is 
an important improvement on 8xx, then we can use an ifdef since 8xx already 
requires its own kernel build.  I'd prefer to see a benchmark showing that it 
actually does make things worse on those chips, though.


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