bit fields && data tearing

[Peter Zijlstra]

On Fri, Sep 05, 2014 at 11:31:09AM -0700, Paul E. McKenney wrote:
> compiler: Allow 1- and 2-byte smp_load_acquire() and smp_store_release()
> 
> CPUs without single-byte and double-byte loads and stores place some
> "interesting" requirements on concurrent code.  For example (adapted
> from Peter Hurley's test code), suppose we have the following structure:
>     
>     	struct foo {
>     		spinlock_t lock1;
>     		spinlock_t lock2;
>     		char a; /* Protected by lock1. */
>     		char b; /* Protected by lock2. */
>     	};
>     	struct foo *foop;
>     
> Of course, it is common (and good) practice to place data protected
> by different locks in separate cache lines.  However, if the locks are
> rarely acquired (for example, only in rare error cases), and there are
> a great many instances of the data structure, then memory footprint can
> trump false-sharing concerns, so that it can be better to place them in
> the same cache cache line as above.
> 
> But if the CPU does not support single-byte loads and stores, a store
> to foop->a will do a non-atomic read-modify-write operation on foop->b,
> which will come as a nasty surprise to someone holding foop->lock2.  So we
> now require CPUs to support single-byte and double-byte loads and stores.
> Therefore, this commit adjusts the definition of __native_word() to allow
> these sizes to be used by smp_load_acquire() and smp_store_release().

So does this patch depends on a patch that removes pre EV56 alpha
support? I'm all for removing that, but I need to see the patch merged
before we can do this.