[question] Can the execution of the atomtic operation instruction pair lwarx/stwcx be interrrupted by local HW interruptions?
w90p710 at gmail.com
Mon Jan 6 17:42:02 EST 2014
On 01/06/2014 02:24 PM, Gavin Hu wrote:
> So, these primitive funcitons like atomic_add() and so on also can't
> prevent processes schedule switch on local CPU core? right?
You are right!
> Gvain. Hu
> On Mon, Jan 6, 2014 at 1:27 PM, wyang <w90p710 at gmail.com
> <mailto:w90p710 at gmail.com>> wrote:
> On 01/06/2014 11:41 AM, Gavin Hu wrote:
>> Thanks your response. :)
>> But that means that these optimitive operations like atomic_add()
>> aren't optimitive actully in PPC architecture, right? Becuase
>> they can be interrupted by loacl HW interrupts. Theoretically,
>> the ISR also can access the atomic gloable variable.
> Nope, my understand is that if you wanna sync kernel primitive
> code with ISR, you have responsibility to disable local
> interrupts. atomic_add does not guarantee to handle such case.
>> The following codes are complete atomic_inc() copied from arch/
>> static __inline__ void atomic_add(int a, atomic_t *v)
>> int t;
>> __asm__ __volatile__(
>> "1: lwarx %0,0,%3 # atomic_add\n\
>> add %0,%2,%0\n"
>> " stwcx. %0,0,%3 \n\
>> bne- 1b"
>> : "=&r" (t), "+m" (v->counter)
>> : "r" (a), "r" (&v->counter)
>> : "cc");
>> Gavin. Hu
>> On Mon, Dec 30, 2013 at 9:54 AM, wyang <w90p710 at gmail.com
>> <mailto:w90p710 at gmail.com>> wrote:
>> On 12/28/2013 01:41 PM, Gavin Hu wrote:
>>> I notice that there is a pair ppc instructions lwarx and
>>> stwcx used to atomtic operation for instance,
>>> In some ppc manuals, they more emphasize its mechanism is
>>> that lwarx can reseve the target memory address preventing
>>> other CORE from modifying it.
>>> I assume that there is atomtic operation executing on the
>>> CORE0 in a multicore system. In this situation, does the
>>> CORE0 disable the local HW interrupt?
>>> Can the executing process from the beginning of lwarx and
>>> end of stwcx be interrupted by HW interruptions/exceptions?
>>> Anyway, they are two assembly instructions.
>> It should just like other arch, the processor should response
>> any interrupt after the execution of a instruction, so the
>> local HW interrupt is not disabled.
>>> Thanks a lot!
>>> "1: lwarx %0,0,%2 # atomic_inc\n\
>>> addic %0,%0,1\n"
>>> " stwcx. %0,0,%2 \n\
>>> Gavin. Hu
>>> Linuxppc-dev mailing list
>>> Linuxppc-dev at lists.ozlabs.org <mailto:Linuxppc-dev at lists.ozlabs.org>
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