[PATCH 2/2] fsl/pci: fix EP device sometimes hangup when system resume from sleep

Scott Wood scottwood at freescale.com
Wed Apr 16 07:11:15 EST 2014

On Tue, 2014-04-15 at 15:43 +0800, Dongsheng Wang wrote:
> From: Wang Dongsheng <dongsheng.wang at freescale.com>
> Root cause is pcie power management state transition need a delay.
> The delay time define in "PCI Bus Power Management Interface Specification".
> D0, D1 or D2 --> D3 need to delay 10ms.
> D3 --> D0 need to delay 10ms.
> Signed-off-by: Wang Dongsheng <dongsheng.wang at freescale.com>

Could you describe the other changes besides the addition of a delay at
the end?


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