[PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
chenhui.zhao at freescale.com
Wed Jun 27 20:10:25 EST 2012
On Tue, Jun 26, 2012 at 09:03:42AM -0500, Kumar Gala wrote:
> On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
> > Do hardware timebase sync. Firstly, stop all timebases, and transfer
> > the timebase value of the boot core to the other core. Finally,
> > start all timebases.
> > Only apply to dual-core chips, such as MPC8572, P2020, etc.
> > Signed-off-by: Zhao Chenhui <chenhui.zhao at freescale.com>
> > Signed-off-by: Li Yang <leoli at freescale.com>
> > ---
> > Changes for v6:
> > * added 85xx_TB_SYNC
> > * added isync() after set_tb()
> > * removed extra entries from mpc85xx_smp_guts_ids
> Why only on dual-core chips? Is this because of something related to 2 cores, or related to corenet vs non-corenet SoCs and how turning on/off the timebase works in the SOC?
> - k
I am working on a timebase sync patch for corenet SoCs which have more than 2 cores.
It is based on this patch.
More information about the Linuxppc-dev