[PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
scottwood at freescale.com
Wed Jun 27 07:45:55 EST 2012
On 06/26/2012 09:03 AM, Kumar Gala wrote:
> On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
>> Do hardware timebase sync. Firstly, stop all timebases, and transfer
>> the timebase value of the boot core to the other core. Finally,
>> start all timebases.
>> Only apply to dual-core chips, such as MPC8572, P2020, etc.
>> Signed-off-by: Zhao Chenhui <chenhui.zhao at freescale.com>
>> Signed-off-by: Li Yang <leoli at freescale.com>
>> Changes for v6:
>> * added 85xx_TB_SYNC
>> * added isync() after set_tb()
>> * removed extra entries from mpc85xx_smp_guts_ids
> Why only on dual-core chips? Is this because of something related to
> 2 cores, or related to corenet vs non-corenet SoCs and how turning
> on/off the timebase works in the SOC?
Some parts are due to corenet versus non-corenet, such as the actual
register you write to to disable/enable the timebase.
There's also a two-core assumption in the synchronization code which
I've complained about multiple times -- although on closer inspection it
looks like this is done under cpu_add_remove_lock, and we can assume
that there's only one core at a time in take_timebase(), regardless of
how many cores are in the system.
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