[PATCH v15 01/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions

[Olof Johansson]

On Fri, Oct 14, 2011 at 03:08:39PM -0700, tmarri at apm.com wrote:
> diff --git a/drivers/usb/dwc/regs.h b/drivers/usb/dwc/regs.h
> new file mode 100644
> index 0000000..d3694f3
> --- /dev/null
> +++ b/drivers/usb/dwc/regs.h

> +#define DWC_GCTL_BSESSION_VALID_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 19))) | ((x) << 19))
> +#define DWC_GCTL_CSESSION_VALID_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 18))) | ((x) << 18))
> +#define DWC_GCTL_DEBOUNCE_RW(reg, x)		\
> +	(((reg) & (~((u32)0x01 << 17))) | ((x) << 17))
> +#define DWC_GCTL_CONN_ID_STATUS_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 16))) | ((x) << 16))
> +#define DWC_GCTL_DEV_HNP_ENA_RW	(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 11))) | ((x) << 11))
> +#define DWC_GCTL_HOST_HNP_ENA_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 10))) | ((x) << 10))
> +#define DWC_GCTL_HNP_REQ_RW(reg, x)		\
> +	(((reg) & (~((u32)0x01 << 9))) | ((x) << 9))
> +#define DWC_GCTL_HOST_NEG_SUCCES_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 8))) | ((x) << 8))
> +#define DWC_GCTL_SES_REQ_RW(reg, x)		\
> +	(((reg) & (~((u32)0x01 << 1))) | ((x) << 1))
> +#define DWC_GCTL_SES_REQ_SUCCESS_RW(reg, x)	\
> +	(((reg) & (~((u32)0x01 << 0))) | ((x) << 0))

Ouch! These could be done much more readable.

> +/*
> + * These Macros represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
> + * GNPTXFSIZ, DPTXFSIZn). Read the register into the u32 element then
> + * read out the bits using the bit elements.
> + */
> +#define DWC_RX_FIFO_DEPTH_RD(reg)	(((reg) & ((u32)0xffff << 16)) >> 16)

What the...   What's wrong with ((reg >> 16) & 0xffff) here and everywhere
else?


-Olof