[PATCH v15 01/10] USB/ppc4xx: Add Synopsys DesignWare HS USB OTG Register definitions

[Pratyush Anand]

On Sat, Oct 15, 2011 at 3:38 AM,  <tmarri at apm.com> wrote:
> From: Tirumala Marri <tmarri at apm.com>
>
[...]

> +/*
> + * These Macros represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
> + * GNPTXFSIZ, DPTXFSIZn). Read the register into the u32 element then
> + * read out the bits using the bit elements.
> + */
> +#define DWC_RX_FIFO_DEPTH_RD(reg)      (((reg) & ((u32)0xffff << 16)) >> 16)
> +#define DWC_RX_FIFO_DEPTH_WR(reg, x)   \
> +       (((reg) & (~((u32)0xffff << 16))) | ((x) << 16))
> +#define DWC_RX_FIFO_START_ADDR_RD(reg)         ((reg) & 0xffff)
> +#define DWC_RX_FIFO_START_ADDR_WR(reg, x)      \
> +       (((reg) & (~((u32)0xffff))) | (x))
> +

These are GNPTX  and DPTX registers.
So name should be DWC_TX_FIFO_DEPTH_RD rather than DWC_RX_FIFO_DEPTH_RD.
Same for other defines.


> +/*
> + * These Macros represents the bit fields in the Non-Periodic Tx FIFO/Queue
> +

[...]

> +#define MAX_PERIO_FIFOS                        15      /* Max periodic FIFOs */
> +#define MAX_TX_FIFOS                   15      /* Max non-periodic FIFOs */
> +
> +/* Maximum number of Endpoints/HostChannels */
> +#define MAX_EPS_CHANNELS 12    /* This come from device tree or defconfig */

There could be some platform even with 16 channels (as specs permits it.)
So, please make it 16.