[PATCH] powerpc/85xx: Setup secondary cores PIR with hard SMP id

[Bhushan Bharat-R65777]

> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org]
> Sent: Thursday, October 20, 2011 9:32 AM
> To: Bhushan Bharat-R65777
> Cc: linuxppc-dev at ozlabs.org
> Subject: Re: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard
> SMP id
> 
> 
> On Oct 19, 2011, at 10:53 PM, Bhushan Bharat-R65777 wrote:
> 
> >
> >
> >> -----Original Message-----
> >> From:
> >> linuxppc-dev-bounces+bharat.bhushan=freescale.com at lists.ozlabs.org
> >> [mailto:linuxppc-dev-
> >> bounces+bharat.bhushan=freescale.com at lists.ozlabs.org] On Behalf Of
> >> bounces+Kumar
> >> Gala
> >> Sent: Friday, October 14, 2011 1:23 PM
> >> To: linuxppc-dev at ozlabs.org
> >> Subject: [PATCH] powerpc/85xx: Setup secondary cores PIR with hard
> >> SMP id
> >>
> >> Normally logical and hard cpu ID are the same, however in same cases
> >> like on the P3060 they may differ.  Where the logical is 0..5, the
> >> hard id goes 0,1,4..7.  This can causes issues for places we utilize
> >> PIR to index into array like in debug exception handlers for finding
> >> the exception stack.
> >
> > Kumar, What should be the CONFIG_NR_CPUS for this? 8 or 6 ?
> 
> 8.

Kumar, I am just trying to understand the impact of setting NR_CPUS = 8 while actual cpus are 6 only.

If I understood correctly, cpu_present, cpu_online are logical cpuid bit map. Also the PACA is allocated for nr_cpu_ids (NR_CPUS) and also indexed by logical cpuid. While they have knowledge of physical_cpuid.

So in this case last two entries of PACA will not be used or wasted?
I am not sure I am missing something here?

Thanks
-Bharat