[PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Zang Roy-R61911]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, November 09, 2011 0:54 AM
> To: Zang Roy-R61911
> Cc: Wood Scott-B07421; linuxppc-dev at lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> PCIe
> 
> On 11/07/2011 11:51 PM, Zang Roy-R61911 wrote:
> >
> >
> >> -----Original Message-----
> >> From: Wood Scott-B07421
> >> Sent: Tuesday, November 08, 2011 2:44 AM
> >> To: Zang Roy-R61911
> >> Cc: linuxppc-dev at lists.ozlabs.org
> >> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive
> for
> >> PCIe
> >>
> >> On 11/07/2011 02:32 AM, Roy Zang wrote:
> >>> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> >>> shared with PCIe controller.
> >>> The silicon internally ties the interrupts to L, so change the
> >>> IRQ[4:6,11] to high level sensitive for PCIe.
> >>
> >> Some extra commentary on why this works would be nice.
> > I do not know what kind of extra commentary you request.
> 
> Just a note that there's magic to allow the PCIe block to output these
> interrupts as either active-high or active-low, depending on how they're
> configured at the mpic.
I do not think there is any magic.
On the contrary, it is the mpic/device tree needs to comply with the hardware setting for the interrupt polarity.

> 
> > IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts
> for PCIe, they need to set high level sensitive.
> > It is clear enough for this patch.
> 
> It's odd enough that I felt the need to go reading through the docs to
> see why such a thing would work at all.
If you consider the normal case, the shared irq pulls up, the PCIe interrupt set to low level sensitive. Anything odd?

> 
> >> The manual says:
> >>
> >>> If a PCI Express INTx interrupt is being used, then the PIC must be
> configured
> >> so that external interrupts
> >>> are level-sensitive (EIVPRn[S] = 1).
> > That is true for all FSL powerpc silicon with PCIe controller beside P1023.
> 
> Sure, my point was more that it didn't say anything there about how to
> configure EIVPRn[P].
It depends on the irq pulls up or down by hardware.
Roy