[PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

[Zang Roy-R61911]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, November 08, 2011 2:44 AM
> To: Zang Roy-R61911
> Cc: linuxppc-dev at lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for
> PCIe
> 
> On 11/07/2011 02:32 AM, Roy Zang wrote:
> > P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> > shared with PCIe controller.
> > The silicon internally ties the interrupts to L, so change the
> > IRQ[4:6,11] to high level sensitive for PCIe.
> 
> Some extra commentary on why this works would be nice.
I do not know what kind of extra commentary you request. 
IRQ 4,5,6, 11 are internally tie to low by silicon. To use these interrupts for PCIe, they need to set high level sensitive.
It is clear enough for this patch.

> 
> The manual says:
> 
> > If a PCI Express INTx interrupt is being used, then the PIC must be configured
> so that external interrupts
> > are level-sensitive (EIVPRn[S] = 1).
That is true for all FSL powerpc silicon with PCIe controller beside P1023.

> 
> and
> 
> > In general, these signals should be considered mutually exclusive. If a PCI
> Express INTx signal is being
> > used, the PIC must be configured so that external interrupts are level
> sensitive (EIVPRn[S] = 1). If an IRQn
> > signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not
> allow inbound PCI Express
> > INTx transactions.
> >
> > Note that it is possible to share IRQn and INTx if the external interrupt is
> level sensitive; however, if an
> > interrupt occurs, the interrupt service routine must poll both the external
> sources connected to the IRQn
> > input and the PCI Express INTx sources to determine from which path the
> external interrupt came. In any
> > case, IRQn should be pulled to the negated state as determined by the
> associated polarity setting in
> > EIVPRn[P].
> 
> So it looks like there's some magic whereby the configuration of the
> MPIC affects how the PCIe feeds the interrupt in.
> 
> Is there (or will there be) an erratum, or anything in the manual
> besides not being documented as external interrupts, about these
> specific interrupts being tied low in silicon or needing to be active high?
I do not think there is (will) an erratum. But I agree the manual needs to document this more clear.
thanks.
Roy