[PATCH 0/1] ppc4xx: Fix PCIe scanning for the 460SX

[Tirumala Marri]

>
> Also, the patch removes the code for waiting for the link to be up with
> a comment "What DCR has the link status on the 460SX?". Please fix that
> (Tirumala, can you provide the missing information ?)
>

It is not one register. Here is the flow for Gen-1.
1. PECFGn_DLLSTA[3] will be asserted when pci-e link comes up.
2. now progream the UTL buffer configuration registers.
3. SW should assert PEUTLn_PCTL[0] to cause flow control initialization.
This is memory mapped using GPL register REGBH , REBAL and REGMSK
4. Now check for the PEUTLN_PSTA[8] for the flow control init completion.
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