[PATCH v2] powerpc32: Kexec support for PPC440X chipsets
Sebastian Andrzej Siewior
bigeasy at linutronix.de
Fri Jul 15 01:40:42 EST 2011
* Suzuki K. Poulose | 2011-07-12 12:14:16 [+0530]:
>Changes from V1: Uses a tmp mapping in the other address space to setup
> the 1:1 mapping (suggested by Sebastian Andrzej Siewior).
>Note: Should we do the same for kernel entry code for PPC44x ?
You have one the kernel mapping. Then you make your temporary mapping
which might be just the one valid TLB entry (after you invalidated the
others). After that you setup multiple mappings to cover 0..2GiB address
space. Since the kernel runs at 0xC.... and you need 0x0.. for the same
memory you end up at some point with two mappings for the same memory.
The reference manual says one should not have two active mappings for
piece of memory. That is why the "other address space" is should be
So I think using this "other address space" for the entry code isn't a
However, I'm fine with this patch.
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